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| am29bl802c data sheet the following document contains information on spansion memory products. although the document is marked with the name of the company that orig inally developed the specification, spansion will continue to offer these products to existing customers. continuity of specifications there is no change to this data sheet as a result of offering the device as a spansion product. any changes that have been made are the result of no rmal data sheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers spansion continues to support existing part number s beginning with ?am? and ?mbm?. to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local sales office for additi onal information about spansion memory solutions. publication number 22371 revision c amendment 7 issue date november 3, 2006
this page left intentionally blank. data sheet this data sheet states amd?s current specifications rega rding the products described herein. this data sheet may be revised by subsequent versions or modifications due to changes in technical specifications. publication# 22371 rev: c amendment: 7 issue date: november 3, 2006 am29bl802c 8 megabit (512 k x 16-bit) cmos 3.0 volt-only burst mode flash memory distinctive characteristics 32 words sequential with wrap around (linear 32), bottom boot one 8 kword, two 4 kword, one 48 kword, three 64 kword, and two 128 kword sectors single power supply operation ? regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors read access times burst access times as fast as 17 ns at industrial temperature range (18 ns at extended temperature range) initial/random access times as fast as 65 ns alterable burst length via baa# pin power dissipation (typical) ? burst mode read: 15 ma @ 25 mhz, 20 ma @ 33 mhz, 25 ma @ 40 mhz ? program/erase: 20 ma ? standby mode, cmos: 3 a 5 v-tolerant data, address, and control signals sector protection ? implemented using in-system or via programming equipment ? temporary sector unprotect feature allows code changes in previously locked sectors unlock bypass program command ? reduces overall programming time when issuing multiple prog ram command sequences embedded algorithms ? embedded erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors ? embedded program algorithm automatically writes and verifies data at specified addresses minimum 100,000 erase cycle guarantee per sector 20-year data retention compatibility with jedec standards ? pinout and software compatible with single- power supply flash ? superior inadvertent write protection ? backward-compatible with amd am29lv and am29f flash memories: powers up in asynchronous mode fo r system boot, but can immediately be placed into burst mode data# polling and toggle bits ? provides a software method of detecting program or erase operation completion ready/busy# pin (ry/by#) ? provides a hardware method of detecting program or erase cycle completion erase suspend/erase resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation hardware reset pin (reset#) ? hardware method to reset the device for reading array data package option ? 56-pin ssop 2 am29bl802c 22371c7 november 3, 2006 data sheet general description the am29bl802c is an 8 mbit, 3.0 volt-only burst mode flash memory devices organized as 524, 288 words. the device is offered in a 56-pin ssop package. these devices are designed to be pro- grammed in-system with the standard system 3.0-volt v cc supply. a 12.0-volt v pp or 5.0 v cc is not required for program or erase operations. the device can also be programmed in standard eprom programmers. the device offers access times of 65, 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. burst mode features the am29bl802c offers a linear burst mode?a 32 word sequential burst with wrap around?in a bottom boot configuration only. this devices require additional control pins for burst operations : load burst address (lba#), burst address advance (baa#), and clock (clk). this implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high perfor- mance read operations. amd flash memory features each device requires only a single 3.0 volt power supply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. the i/o and control signals are 5v tolerant. the am29bl802c is entirely command set compatible with the jedec single-power-supply flash stan- dard . commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device erasure occurs by executing the erase com- mand sequence. this initiates the embedded erase algorithm?an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether a program or erase operation is complete by observing the ry/by# pin, or by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically i nhibits write operations dur- ing power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset # pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the flash memory. the device offers two power-saving features. when ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both these modes. amd?s flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection. november 3, 2006 22371c7 am29bl802c 3 data sheet table of contents this page left intentionally blank. . . . . . . . . . . . . 2 product selector guide . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . 7 device bus operations . . . . . . . . . . . . . . . . . . . . . 8 table 1. device bus operations .......................................................8 requirements for reading array data array in asynchronous (non-burst) mode ..................................................................... 9 requirements for reading ar ray data in synchronous (burst) mode ............................................................................. 9 burst suspend/burst resume operations ................................ 9 ind# end of burst indicator .................................................... 10 writing commands/command sequences ............................ 10 program and erase operation status .................................... 10 standby mode ........................................................................ 10 automatic sleep mode ........................................................... 10 reset#: hardware reset pin ............................................... 10 output disable mode .............................................................. 11 table 2. sector address table ........................................................11 autoselect mode..................................................................... 12 table 3. am29bl802c autoselect codes (high voltage method) ..12 sector protection/unprotection ............................................... 12 figure 1. in-system sector protect/unprotect algorithms ............... 13 temporary sector unprotect .................................................. 14 figure 2. temporary sector unprotect operation........................... 14 hardware data protection . . . . . . . . . . . . . . . . . . 14 low v cc write inhibit .............................................................. 14 write pulse ?glitch? protection ............................................... 14 logical inhibit .......................................................................... 14 power-up write inhibit ............................................................ 14 command definitions . . . . . . . . . . . . . . . . . . . . . 14 reading array data in non-burst mode ................................. 14 reading array data in burst mode ......................................... 15 figure 3. burst mode read with 40 mhz clk, 65 ns t iacc , 18 ns t bacc parameters.................................................................. 15 figure 4. burst mode read with 25 mhz clk, 70 ns t iacc , 24 ns t bacc parameters................................................................. 16 reset command ..................................................................... 16 autoselect command sequence ............................................ 16 program command sequence ............................................... 16 unlock bypass command sequence ..................................... 17 figure 5. program operation .......................................................... 17 chip erase command sequence ........................................... 17 sector erase command sequence ........................................ 18 figure 6. erase operation............................................................... 18 erase suspend/erase resume commands ........................... 18 asynchronous mode ............................................................... 18 burst mode ............................................................................. 19 general ................................................................................... 19 command definitions ............................................................. 20 table 4. am29bl802c command definitions ................................20 write operation status . . . . . . . . . . . . . . . . . . . . 21 dq7: data# polling ................................................................. 21 figure 7. data# polling algorithm .................................................. 21 ry/by#: ready/busy# ............................................................ 22 dq6: toggle bit i .................................................................... 22 dq2: toggle bit ii ................................................................... 22 reading toggle bits dq6/dq2 ............................................... 22 dq5: exceeded timing limits ................................................ 23 dq3: sector erase timer ....................................................... 23 figure 8. toggle bit algorithm........................................................ 23 table 5. write operation status ..................................................... 24 absolute maximum ratings. . . . . . . . . . . . . . . . . 25 figure 9. maximum negative overshoot waveform ...................... 25 figure 10. maximum positive overshoot waveform...................... 25 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 25 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. i cc1 current vs. time (showing active and automatic sleep currents) .............................................................................. 27 figure 12. typical i cc1 vs. frequency ........................................... 27 test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. test setup..................................................................... 28 table 6. test specifications ........................................................... 28 key to switching waveforms .................................................. 28 figure 14. input waveforms and measurement levels ................. 28 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15. conventional read operations timings ....................... 31 figure 16. burst mode read .......................................................... 31 figure 17. reset# timings .......................................................... 32 figure 18. program operation timings.......................................... 34 figure 19. chip/sector erase operation timings .......................... 35 figure 20. data# polling timings (during embedded algorithms). 36 figure 21. toggle bit timings (during embedded algorithms)...... 36 figure 22. dq2 vs. dq6 for erase and erase suspend operations .................................................................... 37 figure 23. temporary sector unprotect timing diagram .............. 37 figure 24. sector protect/unprotect timing diagram .................... 38 figure 25. alternate ce# controlled write operation timings ...... 40 erase and programming performance . . . . . . . . 41 latchup characteristics . . . . . . . . . . . . . . . . . . . . 41 ssop pin capacitance . . . . . . . . . . . . . . . . . . . . . 41 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 physical dimensions*. . . . . . . . . . . . . . . . . . . . . . 42 sso056?56-pin shrink small outline package .................... 42 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 43 revision a (june 1, 1999) ...................................................... 43 revision a+1 (june 25, 1999) ................................................ 43 revision b (november 29, 1999) ............................................ 43 revision c (june 20, 2000) .................................................... 43 revision c+1 (november 16, 2000) ....................................... 43 revision c+2 (july 22, 2002) ................................................. 43 revision c+3 (november 22, 2002) ....................................... 43 revision c+4 (june 4, 2004) .................................................. 44 revision c+5 (february 28, 2005) ......................................... 44 revision c+6 (june 29, 2005) ................................................ 44 revision c7 (november 3, 2006) ........................................... 44 4 am29bl802c 22371c7 november 3, 2006 data sheet product selector guide note: see ?ac characteristics? for full specifications. block diagram family part number am29bl802c speed option regulated voltage range: v cc =3.0?3.6 v 65r 70r 90r 120r temperature range: industrial (i), extended (e) i e i, e i, e i, e max access time, ns (t acc )657090120 max ce# access time, ns (t ce )657090120 max burst access time, ns (t bacc ) 1718242626 burst state counter burst address counter lba# baa# clk v cc v ss state control command register pgm voltage generator v cc detector timer erase voltage generator input/output buffers ind# buffer sector switches chip enable output enable logic y-gating cell matrix address latch y-decoder x-decoder data latch reset# ry/by# ind# stb stb a0?a18 a0?a2 a0?a2 a3, a4 a3, a4 ce# oe# we# dq0?dq15 a0?a4 november 3, 2006 22371c7 am29bl802c 5 data sheet connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 we# reset# ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce# nc v ss oe# dq0 dq8 dq1 dq9 dq2 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 lba# v cc nc nc a8 a9 a10 a11 a12 a13 a14 a15 a16 nc nc v ss dq15 dq7 dq14 dq6 dq13 dq5 23 24 25 26 27 28 dq10 dq3 dq11 v ss clk baa# 34 33 32 31 30 29 dq12 dq4 v cc v cc ind# nc 56-pin ssop 6 am29bl802c 22371c7 november 3, 2006 data sheet pin configuration a0?a18 = 19 addresses dq0?dq15 = 16 data inputs/outputs ce# = chip enable input. this signal shall be asynchronous relative to clk for the burst mode. oe# = output enable input. this signal shall be asynchronous relative to clk for the burst mode. we# = write enable. this signal shall be asynchronous relative to clk for the burst mode. v ss = device ground nc = no connect. pin not connected internally ry/by# = ready busy output clk = clock input that can be tied to the system or microprocessor clock and provides the fundamental timing and internal operating frequency. clk latches input addresses in conjunction with lba# input and increments the burst address with the baa# input. lba# = load burst address input. indicates that the valid address is present on the address inputs. lba# low at the rising edge of the clock latches the address on the address inputs into the burst mode flash device. data becomes available t pac c ns of initial access time after the rising edge of the same clock that latches the address. lba# high indicates that the address is not valid baa# = burst address advance input. increments the address during the burst mode operation baa# low enables the burst mode flash device to read from the next word when gated with the rising edge of the clock. data becomes available t bacc ns of burst access time after the rising edge of the clock baa # high prevents the rising edge of the clock from advancing the data to the next word output. the output data remains unchanged. ind# = highest burst counter address reached. ind# is low at the end of a 32-word burst sequence (when word da + 31 is output). the output will wrap around to da on the next clk cycle (with baa# low). reset# = hardware reset input note: the address, data, and control signals (ry/by#, lba, baa, ind, reset, oe#, ce#, and we#) are 5 v tolerant. logic symbol 19 16 dq0?dq15 a0?a18 ce# oe# we# reset# clk ry/by# ind# lba# baa# november 3, 2006 22371c7 am29bl802c 7 data sheet ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combi- nation) is formed by a combination of the elements below. for information on full voltage range options (2.7?3.6 v), please contact amd. valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. am29bl802c b65rz i temperature range i = industrial (?40 c to +85 c) e = extended (?40 c to +125 c) f = industrial (?40 c to +85 c) for pb-free package k = extended (?40 c to +125 c) for pb-free package package type z = 56-pin shrink small outline package (sso056) speed option see product selector guide and valid combinations boot code sector architecture b = bottom sector device number/description am29bl802c 8 megabit (512 k x 16-bit) cmos high performance burst mode flash memory 3.0 volt-only read, program, and erase valid combinations am29bl802cb-65r zi, ze, zf, zk am29bl802cb-70r zi, ze, zf, zk am29bl802cb-90r zi, ze, zf, zk am29bl802cb-120r zi, ze, zf, zk 8 am29bl802c 22371c7 november 3, 2006 data sheet device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register it- self does not occupy any addressable memory loca- tion. the register is composed of latches that store the commands, along with the address and data informa- tion needed to execute the command. the contents of the register serve as inputs to the internal state ma- chine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. device bus operations legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. notes: 1. addresses are a18:a0. 2. the sector protect and sector unprotect functions may al so be implemented via programming equipment. see the ?sector protection/unprotection? section. operation ce# oe# we# reset# clk lba# baa# addresses (note 1) data (dq0?dq15) read l l h h x x x a in d out write l h l h x x x a in d in standby v cc 0.3 v xx v cc 0.3 v xxx x high z output disable l h h h x x x high z high z reset x x x l x x x x high z sector protect (note 2) l h l v id xxx sector address, a6 = l, a1 = h, a0 = l d in sector unprotect (note 2) l h l v id xxx sector address, a6 = h, a1 = h, a0 = l d in temporary sector unprotect x x x v id xxx a in high z burst read operations load starting burst address l x h h l h a in x advance burst to next address (no data presented on the data bus lhh h hl x high z advance burst to next address (appropriate data presented on the data bus llh h hl x data out dq0-dq15 terminate current burst read cycle h x h h x x x high z terminate current burst read cycle; start new burst read cycle lxh h lh a in x burst suspend: (all data is retained internally in the device) lhh h xhh x high z burst resume: (same data as burst suspend) llh h hh x data out dq0?dq15 burst resume: (incremented data from burst suspend) llh h hl x data out dq0?dq15 november 3, 2006 22371c7 am29bl802c 9 data sheet requirements for reading array data array in asynchronous (non-burst) mode to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should re- main at v ih . address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable addresses and stable ce# to valid data at the output pins. the output enable access time is the delay from the falling edge of oe# to valid data at the output pins (assuming the addresses have been stable for at least t acc ?t oe time). the internal state machine is set for reading array data in the upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that as- sert valid addresses on the device address inputs pro- duce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data in non-burst mode? for more information. refer to the ac read operations table for timing specifications and to figure 15 for the timing di- agram. i cc1 in the dc characteristics table represents the active current specification for reading array data. requirements for reading array data in synchronous (burst) mode the device offers fast 32-word sequential burst reads and is used to support microprocessors that implement an instruction prefetch queue, as well as large data transfers during system configuration. three additional pins?load burst address (lba#), burst address advance (baa#), and clock (clk)? allow interfacing to microprocessors and microcontrol- lers with minimal glue logic. burst mode read is a syn- chronous operation tied to the rising edge of clk. ce#, oe#, and we# are asynchronous (relative to clk). when the device is in asynchronous mode (after power-up or reset# pulse), any signals on the clk, lba#, and baa# inputs are ignored. the device oper- ates as a conventional flash device, as described in the previous section. to enable burst mode operat ion, the system must issue the burst mode enable command sequence (see table 4). after the device has entered the burst mode, the system must assert load burst address (lba#) low for one clock period, which loads the starting address into the device. the first burst data is available after the initial access time (t iacc ) from the rising edge of the clk that loads the burst address. after the initial access, subsequent burst data is available t bacc after each rising edge of clk. the device increments the address at each rising edge of the clock cycles while baa# is asserted low. the 5- bit burst address counter is set to 00000b at the starting address. when the burst address counter is reaches 11111b , the device outputs the last word in the burst sequence, and outputs a low on ind#. if the system continues to assert baa#, on the next clk the device will output the data for the starting address?the burst address counter will have ?wrapped around? to 00000b. for example, if the initial address is xxxx0h, the data order will be 0- 1-2-3.....28-29-3 0-31-0-1...; if the initial address is xxxx2h, the data order will be 2-3- 4-5.....28-29-30-31-0-1-2-3...; if the initial address is xxxx8h, the data order will be 8-9-10-11.....30-31-0-1- 2-3-4-5-6-7-8-9....; and so on. data will be repeated if more than 32 clocks are supplied , and baa# remains asserted low. a burst mode read operation is terminated using one of three methods: ? in the first method, ce# is asserted high. the device in this case remains in burst mode; asserting lba# low terminates the previous burst read cycle and starts a new burst read cycle with the address that is currently valid. ? in the second method, the burst disable command sequence is written to the device. the device halts the burst operation and returns to the asynchronous mode. ? in the third method, reset # is asserted low. all opertations are immediately terminated, and the device will revert to the asynchronous mode. note that writing the rese t command will not terminate the burst mode. burst suspend/burst resume operations the device offers burst suspend and burst resume operations. when both oe# and baa# are taken high, the device removes (?suspends?) the data from the outputs (because oe# is high), but ?holds? the data internally. the device resumes burst operation when either oe# and/or baa# is asserted low. asserting the oe# only causes the device to present the same data that was held during the burst suspend operation. as long as baa# is high, the device will continue to output that word of data. asserting both oe# and baa# low resumes the burst operation, and on the next rising edge of clk, increments the counter and outputs the next word of data. 10 am29bl802c 22371c7 november 3, 2006 data sheet ind# end of burst indicator the ind# output signal goes low when the device is ouputting the last word of a 32-word burst sequence (word da+31). when the starting address was loaded with lba#, the 5-bit burst address counter was set to 00000b. the counter increments to 11111b on the 32nd word in the burst sequence. if the system con- tinues to assert baa# low, on the next clk the device will output the starting address data (da). the burst address counter will be agai n set to 00000b, and will have ?wrapped around.? writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sec- tors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facili- tate faster programming. once the device enters the un- lock bypass mode, only two write cycles are required to program a word, instead of four. the ?program com- mand sequence? section has details on programming data to the device using both standard and unlock by- pass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 2 indicates the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. the ?command definitions? section has details on erasing a sector or the entire chip, or suspending/re- suming the erase operation. after the system writes the autoselect command se- quence, the device enters t he autoselect mode. the sys- tem can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? and ?autoselect command sequence? sections for more information. i cc2 in the dc characteristi cs table represents the ac- tive current specification for the write mode. the ?ac characteristics? section cont ains timing specification ta- bles and timing diagrams for write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on dq7?dq0. standard read cycle timings and i cc read specifications apply. refer to ?write operation sta- tus? for more information, and to ?ac characteristics? for timing diagrams. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the de- vice is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. in the dc characteristics table, i cc3 and i cc4 represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics table represents the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of reset- ting the device to reading array data. when the system drives the reset# pin to v il for at least a period of t rp , the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. if reset# is asserted during a program or erase oper- ation, the ry/by# pin remains a ?0? (busy) until the inter- nal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset op- eration is complete. if reset# is asserted when a pro- november 3, 2006 22371c7 am29bl802c 11 data sheet gram or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to the ac characteristics tables for reset# pa- rameters and to figure 17 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high imped- ance state. table 2. sector address table sector a18 a17 a16 a15 a14 a13 a12 sector size address range sa0 0 0 0 0 0 0 x 8 kwords 00000h?01fffh sa1 0 0 0 0 0 1 0 4 kwords 02000h?02fffh sa2 0 0 0 0 0 1 1 4 kwords 03000h?03fffh sa3 0 0 0 01, 11 x x 48 kwords 04000h?0ffffh sa4 0 0 1 x x x x 64 kwords 10000h?1ffffh sa5 0 1 0 x x x x 64 kwords 20000h?2ffffh sa6 0 1 1 x x x x 64 kwords 30000h?3ffffh sa7 1 0 x x x x x 128 kwords 40000h?5ffffh sa8 1 1 x x x x x 128 kwords 60000h?7ffffh 12 am29bl802c 22371c7 november 3, 2006 data sheet autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in table 1. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see table 2). table 1 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the program- ming equipment may then read the corresponding identifier code on dq7-dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 4. this method does not require v id . see ?command definitions? for details on using the autoselect mode. table 3. am29bl802c autoselect codes (high voltage method) l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. note: the autoselect codes may also be accessed in-system via command sequences. see table 4. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hard- ware sector unprotection feature re-enables both program and erase operations in previously protected sectors. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is protected or unprotected. see ?autoselect mode? for details. sector protection/unprotection can be implemented via two methods. the primary method requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 1 shows the algo- rithms and figure 24 shows the timing diagram. this method uses standard microprocessor bus cycle timing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the alternate method intended only for programming equipment requires v id on address pin a9 and oe#. this method is compatible with programmer routines written for earlier 3.0 volt-only amd flash devices. de- tails on this method are provided in a supplement, pub- lication number 22372, available on www.spansion.com . description ce# oe# we# a18 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq7 to dq0 manufacturer id : amd l l h x x v id xlxll 0001h device id: am29bl802cb (bottom boot block) llhxxv id xlxlh 0081h sector protection verification l l h sa x v id xlxhl 0001h (protected) 0000h (unprotected) burst mode status l l h x x v id xlxhh 0000h (non-burst mode) 0001h (burst mode) november 3, 2006 22371c7 am29bl802c 13 data sheet figure 1. in-system sector protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1 14 am29bl802c 22371c7 november 3, 2006 data sheet temporary sector unprotect this feature allows temporary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the re- set# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the re- set# pin, all the previously protected sectors are protected again. figure 2 shows the algorithm, and figure 23 shows the timing diagrams, for this feature. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 4 for com- mand definitions). in addition, the following hardware data protection measures pr event accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent uninten- tional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to reading array data on power-up. command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. table 4 defines the valid register command sequences. writing incorrect address and data val- ues or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appropriate timing diagrams in the ac characteristics section. reading array data in non-burst mode the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or em- bedded erase algorithm. after the device accepts an erase suspend com- mand, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming opera- tion in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? for more information on this mode. the system must issue the reset command to re-en- able the device for reading array data if dq5 goes high, start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. figure 2. temporary sector unprotect operation november 3, 2006 22371c7 am29bl802c 15 data sheet or while in the autoselect mode. see the ?reset com- mand? section, next. see also ?requirements for reading array data array in asynchronous (non-burst) mode? in the ?key to switch- ing waveforms? section for more information. the read operations table provides the read parameters, and fig- ure 15 shows the timing diagram. reading array data in burst mode the device powers up in the non-burst mode. to read array data in burst mode, the system must write the four-cycle burst mode enable command sequence (see table 4). the device then enters burst mode. in addition to asserting ce#, oe#, and we# control sig- nals, burst mode operation requires that the system provide appropriate lba#, baa#, and clk signals. for successful burst mode reads, the following events must occur (refer to figures 3 and 4 for this discussion): 1. the system asserts lba# low, indicating to the de- vice that a valid initial burst address is available on the address bus. lba# must be kept low until at least the next rising edge of the clk signal, upon which the device loads the initial burst address. 2. the system returns lba# to a logic high. the device requires that the next rising edge of clk occur with lba# high for proper burst mode operation. typi- cally, the initial number of clk cycles depends on the clock frequency and the rated speed of the de- vice. 3. after the initial data has been read, the system as- serts baa# low to indicate it is ready to read the re- maining burst read cycles. each successive rising edge of the clk signal then causes the flash device to increment the burst address and output sequen- tial burst data. 4. when the device outputs the last word of data in the 32-word burst mode read sequence, the device out- puts a logic low on the ind# pin. this indicates to the system that the burst mode read sequence is complete. 5. to exit the burst mode, the system must write the four-cycle burst mode disable command sequence. the device will also exit the burst mode if powered down or if reset# is a sserted. the device will not exit the burst mode if the reset command is written. figure 3. burst mode read with 40 mhz clk, 65 ns t iacc , 18 ns t bacc parameters clk lba# baa# data oe# step 1 step 2 step 3 25 ns 25 ns 25 ns 25 ns 65 ns 25 ns 18 ns da da +1 da +2 18 ns 16 am29bl802c 22371c7 november 3, 2006 data sheet figure 4. burst mode read with 25 mhz clk, 70 ns t iacc , 24 ns t bacc parameters reset command writing the reset command to the device resets the de- vice to reading array data. address bits are don?t care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence be- fore programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to read ing array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during erase suspend). see ?ac characteristics? for parameters, and to figure 17 for the timing diagram. autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. table 4 shows the address and data requirements. this method is an alternative to that shown in table 1, which is intended for prom programmers and requires v id on address bit a9. the autoselect command seque nce is initiated by writ- ing two unlock cycles, followed by the autoselect com- mand. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address 00h retrieves the manufacturer code. a read cycle at address 01h returns the device code. a read cycle containing a sector address (sa) and the address 02h in word mode returns 0001h if that sector is protected, or 0000h if it is unprotected. refer to table 2 for valid sector addresses. a read cycle at address 03h returns 0000h if the device is in asynchro- nous mode, or 0001h if in synchronous (burst) mode. the system must write the reset command to exit the autoselect mode and return to reading array data. program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically gener- ates the program pulses and verifies the programmed cell margin. table 4 shows the address and data re- quirements for the program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7, dq6, or ry/by#. see ?write operation status? for in- formation on these status bits. clk lba# baa# data step 1 step 2 step 3 40 ns 40 ns 40 ns 40 ns 70 ns 40 ns 24 ns da da +1 24 ns da +2 da +3 24 ns oe# november 3, 2006 22371c7 am29bl802c 17 data sheet any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program- ming operation. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempting to do so may halt the operation and set dq5 to ?1,? or cause the data# polling algorithm to indicate the operation was suc- cessful. however, a succeedin g read will show that the data is still ?0?. only erase operations can convert a ?0? to a ?1?. unlock bypass command sequence the unlock bypass feature allows the system to pro- gram words to the device faster than using the standard program command sequence. the unlock bypass com- mand sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then en- ters the unlock bypass mode. a two-cycle unlock by- pass program command sequence is all that is required to program in this mode. the first cycle in this se- quence contains the unlock bypass program com- mand, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. table 4 shows the requirements for the com- mand sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cy cle must contain the data 90h; the second cycle the data 00h. addresses are don?t care for both cycles. the device then returns to reading array data. figure 5 illustrates the algor ithm for the program oper- ation. see the erase/program operations table in ?ac characteristics? for parameters, and to figure 18 for timing diagrams. note: see table 4 for program command sequence. figure 5. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 4 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embed- ded erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately ter- minates the operation. the chip erase command se- quence should be reinitiated once the device has returned to reading array data, to ensure data integrity. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress 18 am29bl802c 22371c7 november 3, 2006 data sheet the system can determine the status of the erase op- eration by using dq7, dq6, dq2, or ry/by#. see ?write operation status? for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 6 illustrates the algorithm for the erase opera- tion. see the erase/program operations tables in ?ac characteristics? for parameters, and to figure 19 for timing diagrams. sector erase co mmand sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un- lock cycles, followed by a set-up command. two addi- tional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. table 4 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time be- tween these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must rewrit e the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see the ?dq3: sector erase timer? section.) the time-out begins from the rising edge of the final we# pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation immediately terminates the op- eration. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the sta- tus of the erase operation by using dq7, dq6, dq2, or ry/by#. (refer to ?write operation status? for informa- tion on these status bits.) figure 6 illustrates the algorithm for the erase opera- tion. refer to the erase/program operations tables in the ?ac characteristics? section for parameters, and to figure 19 for timing diagrams. notes: 1. see table 4 for erase command sequence. 2. see ?dq3: sector erase timer? for more information. figure 6. erase operation erase suspend/erase resume commands the erase suspend command allows the system to in- terrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the erase suspend command has a different effect depending on whether the flash device is in asynchronous mode or burst mode. asynchronous mode the erase suspend command is only valid when the flash device is in asynchronous mode. during erase suspend operation asynchronous read/program oper- ations behave normally in non-erasing sectors. how- ever, erase suspend operation prevents the flash start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress november 3, 2006 22371c7 am29bl802c 19 data sheet device from entering burst mode. to enter burst mode either the erase operation must be allowed to complete normally, or it can be prematurely terminated by issuing a hardware reset. burst mode while in burst mode the erase suspend command is ignored and the device continues to operate normally in burst mode. if erase suspend operation is required, then burst mode must be terminated and asynchro- nous mode initiated. general this command is valid only during the sector erase op- eration, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase op- eration or embedded program algorithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. addresses are ?don?t-cares? when writing the erase suspend com- mand. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sec- tor erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) normal read and write timings and command definitions apply. note that burst read is not available when the device is erase-suspended. only asynchronous reads are al- lowed. reading at any address within erase-sus- pended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase- suspended. see ?write operation status? for informa- tion on these status bits. after an erase-suspended program operation is com- plete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program oper- ation. see ?write operation status? for more informa- tion. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see ?autoselect command sequence? for more information. the system must write the erase resume command (address bits are ?don?t care?) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the de- vice has resumed erasing. 20 am29bl802c 22371c7 november 3, 2006 data sheet command definitions table 4. am29bl802c command definitions legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a18?a12 uniquely select any sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t cares for unlock and command cycles. 5. address bits a18?a11 are don?t cares for unlock and command cycles, unless sa or pa required. 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 8. the fourth cycle of the autoselect command sequence is a read cycle. 9. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more information. 10. the data is 00h if the device is in asynchronous mode and 01h if in synchronous (burst) mode. 11. the unlock bypass command is required prior to the unlock bypass program command. 12. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 13. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 14. the erase resume command is valid only during the erase suspend mode. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id 4 555 aa 2aa 55 555 90 x00 01 device id, bottom boot block 4 555 aa 2aa 55 555 90 x01 2281 sector protect verify (note 9) 4 555 aa 2aa 55 555 90 (sa) x02 0000 0001 burst mode status (note 10) 4 555 aa 2aa 55 555 90 x03 0000 0001 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 11) 2 xxx a0 pa pd unlock bypass reset (note 12) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 13) 1 xxx b0 erase resume (note 14) 1 xxx 30 burst mode burst mode enable 4 555 aa 2aa 55 555 c0 xxx 01 burst mode disable 4 555 aa 2aa 55 555 c0 xxx 00 november 3, 2006 22371c7 am29bl802c 21 data sheet write operation status the device provides several bits to determine the sta- tus of a write operation: dq2, dq3, dq5, dq6, dq7, and ry/by#. table 5 and the following subsections de- scribe the functions of these bits. dq7, ry/by#, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or com- pleted, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to pro- gramming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pr ogram address falls within a protected sector, data# polling on dq7 is active for ap- proximately 1 s, then the device returns to reading array data. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase al- gorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. this is analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to ?1?; prior to this, the device outputs the ?complement,? or ?0.? the system must provide an address within any of the sectors selected for erasure to read valid status in- formation on dq7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the de- vice returns to reading arra y data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7? dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. figure 20, data# polling timings (during embed ded algorithms), in the ?ac characteristics? se ction illustrates this. table 5 shows the outputs for data# polling on dq7. figure 7 shows the data# polling algorithm. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 7. data# polling algorithm 22 am29bl802c 22371c7 november 3, 2006 data sheet ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. table 5 shows the outputs for ry/by#. figures 15, 17, 18 and 19 shows ry/by# for read, reset, program, and erase operations, respectively. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase op- eration), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cy cles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycl es.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sec- tors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the em- bedded erase algorithm erases the unprotected sec- tors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to deter- mine whether a sector is acti vely erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on ?dq7: data# polling?). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 5 shows the outputs for toggle bit i on dq6. fig- ure 8 shows the toggle bit algorithm in flowchart form, and the section ?reading toggle bits dq6/dq2? ex- plains the algorithm. figure 21 in the ?ac characteris- tics? section shows the toggle bit timing diagrams. figure 22 shows the differences between dq2 and dq6 in graphical form. see also the subsection on ?dq2: toggle bit ii?. dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# to con- trol the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 5 to compare outputs for dq2 and dq6. figure 8 shows the toggle bit algorithm in flowchart form, and the section ?reading toggle bits dq6/dq2? explains the algorithm. see also the dq6: toggle bit i subsection. figure 21 shows the toggle bit timing dia- gram. figure 22 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 8 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initia l two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system november 3, 2006 22371c7 am29bl802c 23 data sheet must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 8). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified intern al pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has ex- ceeded the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out is complete, dq3 switches from ?0? to ?1.? the system may ignore dq3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. see also the ?sector erase command sequence? section. after the sector erase command sequence is written, the system should read the status on dq7 (data# poll- ing) or dq6 (toggle bit i) to ensure the device has ac- cepted the command sequence, and then read dq3. if dq3 is ?1?, the internally controlled erase cycle has be- gun; all further commands (other than erase suspend) are ignored until the erase operation is complete. if dq3 is ?0?, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been ac- cepted. table 5 shows the outputs for dq3. start no yes yes dq5 = 1? no yes dq6 = toggle? no read byte (dq0-dq7) address = va dq6 = toggle? read byte twice (dq 0-dq7) adrdess = va read byte (dq0-dq7) address = va fail pass notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to ?1?. see text. figure 8. toggle bit algorithm (note 1) (notes 1, 2) 24 am29bl802c 22371c7 november 3, 2006 data sheet table 5. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedde d erase operation has exceeded the maximum timing limits. see ?dq5: exceeded timing limits? for more information. 2. dq7 and dq2 require a valid address when reading status inform ation. refer to the appropriate subsection for further details. operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0 november 3, 2006 22371c7 am29bl802c 25 data sheet absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied. . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9 , oe# , and reset# (note 2) . .?0.5 v to +13.0 v all other pins (note 1). . . . . . . . . . . ?0.5 v to +5.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input and i/o pins is ?0.5 v. during voltage transitions, input and i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 9. maximum dc voltage on output and i/os is v cc + 0.5 v. during voltage transitions input and i/os may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 10. 2. minimum dc input voltage on pins a9, oe#, and reset# is -0.5 v. during voltage transitions, a9, oe#, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 9. maximum dc input voltage on pin a9 and oe# is +13.0 v which may overshoot to 14.0 v for periods up to 20 ns. 3. 3.no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. 4.stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the de- vice at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating condi- tions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c extended (e) devices ambient temperature (t a ) . . . . . . . . ?40c to +125c v cc supply voltages v cc for regulated voltage range. . . . . . . 3.0 v to 3.6 v operating ranges define those li mits between which the func- tionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 9. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 10. maximum positive overshoot waveform 26 am29bl802c 22371c7 november 3, 2006 data sheet dc characteristics cmos compatible notes: 1. the i cc current listed is typically le ss than 2 ma/mhz, with oe# at v ih . typical v cc is 3.0 v. 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 3 a. 5. 32-word average. 6. not 100% tested. parameter description test conditions min typ max unit i li input load current v in = v ss to 5.5 v, v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to 5.5 v, v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1, 2) ce# = v il, oe# = v ih , 5 mhz 9 16 ma i cc2 v cc active write current (notes 2, 3, 6) ce# = v il, oe# = v ih 20 30 ma i cc3 v cc standby current (not e 2) ce#, reset# = v cc 0.3 v 3 10 a i cc4 v cc standby current during reset (note 2) reset# = v ss 0.3 v 3 10 a i cc5 automatic sleep mode (notes 2, 4) v ih = v cc 0.3 v; v il = v ss 0.3 v oe# = v ih 310a oe# = v il 820a i cc6 v cc burst mode read current (notes 2, 5) ce# = v il, oe# = v ih 25 mhz 15 30 ma 33 mhz 20 35 ma 40 mhz 25 40 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7 x v cc 5.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.3 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ? 2.0 ma, v cc = v cc min 0.85 x v cc v v oh2 i oh = ? 100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage (note 4) 2.3 2.5 v november 3, 2006 22371c7 am29bl802c 27 data sheet dc characteristics (continued) zero power flash note: addresses are switching at 1 mhz figure 11. i cc1 current vs. time (showing active and automatic sleep currents) 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 12345 frequency in mhz supply current in ma note: t = 25 c figure 12. typical i cc1 vs. frequency 2.7 v 3.6 v 4 6 28 am29bl802c 22371c7 november 3, 2006 data sheet test conditions table 6. test specifications key to switching waveforms 2.7 k c l 6.2 k 3.3 v device under te s t figure 13. test setup note: diodes are in3064 or equivalent test condition 65r, 70r 90r, 120r unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input figure 14. input waveforms and measurement levels november 3, 2006 22371c7 am29bl802c 29 data sheet ac characteristics read operations notes: 1. not 100% tested. 2. see figure 13 and table 6 for test specifications parameter description test setup speed options and temperature ranges unit jedec std. 65r 70r 90r 120r i e i, e i, e i, e t avav t rc read cycle time (note 1) min 65 70 90 120 ns t avqv t acc address to output delay ce# = v il oe# = v il max 65 70 90 120 ns t elqv t ce chip enable to output delay oe# = v il max 65 70 90 120 ns t glqv t oe output enable to output delay max 17 18 24 26 26 ns t ehqz t df chip enable to output high z (note 1) max 17 18 24 26 26 ns t ghqz t df output enable to output high z (note 1) max 20 25 30 30 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 1) min 0 ns 30 am29bl802c 22371c7 november 3, 2006 data sheet ac characteristics burst mode read note: initial valid data will be output after second clock rising edge of lba# assertion. parameter description speed options and temperature ranges unit jedec std. 65r 70r 90r 120r i e i, e i, e i, e t iacc initial access time lba# valid clock to output delay (see note) max 65 70 90 120 ns t bacc burst access time baa# valid clock to output delay max1718242626ns t lbas lba# setup time min 6 ns t lbah lba# hold time min 2 ns t baas baa# setup time min 6 ns t baah baa# hold time min 2 ns t bdh data hold time from next clock cycle max 4 ns t acs address setup time to clk (see note) min 6 ns t ach address hold time from clk (see note) min 2 ns t oe output enable to output valid max 17 18 24 26 26 ns t oez output enable to output high z max 20 25 30 30 ns t cez chip enable to output high z min 20 25 30 30 ns t ces ce# setup time to clock min 6 ns november 3, 2006 22371c7 am29bl802c 31 data sheet ac characteristics figure 15. conventional read operations timings figure 16. burst mode read t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v ry/by# reset# t df t oh da da + 2 da + 3 da + 31 oe#* dq0: dq15 a0: a18 aa ind# baa# lba# clk ce# t ces t baas t baah t acs t lbas t lbah t ach t oe t bacc t bdh t oez t cez t iacc da + 1 32 am29bl802c 22371c7 november 3, 2006 data sheet ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options jedec std test setup unit t ready reset# pin low (during embedded algorithms) to read or write (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb figure 17. reset# timings november 3, 2006 22371c7 am29bl802c 33 data sheet ac characteristics erase/program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter speed options jedec std description 65r 70r 90r 120r unit t avav t wc write cycle time (note 1) min 65 70 90 120 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 45 45 45 50 ns t dvwh t ds data setup time min35354550ns t whdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 35 35 50 ns t whwl t wph write pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) typ 9 s t whwh2 t whwh2 sector erase operation (note 2) typ 1 sec t vcs v cc setup time (note 1) min 50 s t rb recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns 34 am29bl802c 22371c7 november 3, 2006 data sheet ac characteristics note: pa = program address, pd = program data, d out is the true data at the program address. figure 18. program operation timings oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa november 3, 2006 22371c7 am29bl802c 35 data sheet ac characteristics note: sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status?). figure 19. chip/sector erase operation timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy 36 am29bl802c 22371c7 november 3, 2006 data sheet ac characteristics we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle afte r command sequence, last status read cycle, and array data read cycle. figure 20. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe dq6/dq2 ry/by# t busy addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. figure 21. toggle bit timings (during embedded algorithms) november 3, 2006 22371c7 am29bl802c 37 data sheet ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std. description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s note: the system may use ce# or oe# to toggle dq2 and dq 6. dq2 toggles only when read at an address within an erase-suspended sector. figure 22. dq2 vs. dq6 for erase and erase suspend operations enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing reset# t vidr 12 v 0 or 3 v ce# we# ry/by# t vidr t rsp program or erase command sequence figure 23. temporary sector unprotect timing diagram 38 am29bl802c 22371c7 november 3, 2006 data sheet ac characteristics sector protect: 150 s sector unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector protect/unprotect verify v id v ih note: for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. figure 24. sector protect/unprotect timing diagram november 3, 2006 22371c7 am29bl802c 39 data sheet ac characteristics alternate ce# cont rolled erase/pr ogram operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter speed options jedec std description 65r 70r 90r 120r unit t avav t wc write cycle time (note 1) min 65 70 90 120 ns t avel t as address setup time min 0 ns t elax t ah address hold time min45454550ns t dveh t ds data setup time min35354550ns t ehdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 35 35 50 ns t ehel t cph ce# pulse width high min 30 ns t whwsh1 t whwh1 programming operation (note 2) typ 9 s t whwh2 t whwh2 sector erase operation (note 2) typ 1 sec 40 am29bl802c 22371c7 november 3, 2006 data sheet ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. pa = program address, pd = program data, dq7# = complement of the data written to the device, d out = data written to the device. 2. figure indicates the last two bus cycles of the command sequence. figure 25. alternate ce# controlled write operation timings november 3, 2006 22371c7 am29bl802c 41 data sheet erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 100,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 3.0 v, 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 4 for further information on command definitions. 6. the device has a minimum erase and pr ogram cycle endurance of 1 million cycles. latchup characteristics includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. ssop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention * for reference only. bsc is an ansi standard for basic space centering. parameter typ (note 1) max (note 2) unit comments sector erase time 5 15 s excludes 00h programming prior to erasure (note 4) chip erase time 45 s word programming time 9 360 s excludes system level overhead (note 5) chip programming time (note 3) 9 27 s description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf parameter test conditions min unit minimum pattern data retention time 150 c10 years 125 c20 years 42 am29bl802c 22371c7 november 3, 2006 data sheet physical dimensions* sso056?56-pin shrink small outline package dwg rev ab; 10/99 november 3, 2006 22371c7 am29bl802c 43 data sheet revision summary revision a (june 1, 1999) initial release. revision a+1 (june 25, 1999) general description corrected the device density in the first paragraph. command definitions reading array data in burst mode: added reference to figure 3 in the first paragraph. revision b (november 29, 1999) global all speed options are now offered only at the regulated voltage range of 3.0 to 3.6 v. the 90 and 120 speed options now have a t oe of 26 ns at the industrial tem- perature range. the 70 ns speed option is now avail- able at the extended temperature range. ac characteristics in figures 17 and 18, deleted t ghwl ; modified oe# waveform. physical dimensions updated drawing of ssop to new version. revision c (june 20, 2000) global the ?advance information? data sheet designation has been changed to ?preliminary.? only minor parameter changes, if any, may occur. speed, package, and tem- perature range combinations may also change in future data sheet revisions. distinctive characteristics changed burst access time specification for the 65r speed option in the industrial temperature range from 19 to 18 ns. product selector guide replaced t oe with t bacc to more clearly distinguish burst mode access from asynchronous access times. note however, that in burst mode, t oe and t bacc spec- ifications are identical. changed t bacc for the 65r speed option in the industrial temperature range from 19 to 18 ns. ordering information burn-in processing is no longer available. requirements for reading array data array in asynchronous (non-burst) mode clarified the description of how to terminate a burst mode read operation. burst mode read with 40 mhz clk figure changed t bacc for the 65r speed option in the indus- trial temperature range from 19 to 18 ns. read operations table changed t oe and t df for the 65r speed option in the industrial temperature range from 19 to 18 ns. burst mode read table changed t oe and t bacc for the 65r speed option in the industrial temperature range from 19 to 18 ns. burst mode read figure corrected baa# waveform to return high before the final clock cycle shown. erase and programming performance table, erase and program operations table, alternate ce# con- trolled erase and program operations table resolved differences in typical sector erase times. the typical sector erase time for all sectors is 3 sec. revision c+1 (november 16, 2000) global deleted preliminary status from document. added table of contents. added figure 1, in-system sector protect/unprotect algorithms figure to document (was missing from previous revisions). revision c+2 (july 22, 2002) pin description, ind# end of burst indicator clarified description of ind# function. table 1, device bus operations in burst read operations se ction, changed baa# to ?h? for ?load starting burst address? and terminate current burst read cycle; start new burst read cycle.? requirements for reading array data in synchro- nous (burst) mode modified section to clarify the description of the ind# and burst read functions. burst sequence table deleted table. revision c+3 (november 22, 2002) distinctive characteristics changed endurance to 1 million cycles. erase suspend/erase resume command sequence noted that only asynchronous reads are allowed during the erase suspend mode, added asynchronous mode and burst mode section. 44 am29bl802c 22371c7 november 3, 2006 data sheet erase/program operations table, alternate ce# controlled erase/program operations table changed typical sector erase time from 3 s to 1 s. erase and programming performance changed typical/maximum sector erase time from 3 s/60 s to 5 s/15 s, respectively. changed typical chip erase time from 22 s to 45 s. changed endurance to 1 million cycles. revision c+4 (june 4, 2004) ordering information changed extended temperature range to -40 c. operating ranges changed extended temperature range to -40 c. revision c+5 ( february 28, 2005) ordering information changed extended temperature range to -55 c. added pb-free package information. valid combinations table added pb-free combinations . revision c+6 (june 29, 2005) distinctive characteristics changed bullet point value from 1,000,000 to 100,000. erase and programming performance changed values for ?sector erase time? and ?chip erase time? parameters. adjusted notes values from 1,000,000 to 100,000. ordering information changed extended temperature range to -40c. revision c7 (november 3, 2006) sector protection/unprotection corrected reference to programming supplement pub- lication number and location. erase and program operations table changed t busy to a maximum specification. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limita- tion, ordinary industrial use, general o ffice use, personal use, and household use, but are not designed, developed and manufac tured as con- templated (1) for any use that includes fatal risks or dangers th at, unless extremely high safety is secured, could have a seri ous effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolera ble (i.e., submersible repeater and artifici al satellite). please note that spansion inc. will not be liable to you and/or any third party for any claims or damages arisi ng in connection with above-mentioned uses of the products. any se miconductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and pr evention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on expor t under the foreign exchange and foreign trade law of japan, the us export administra tion regulations or the applicable laws of any other country, the prior au- thorization by the respective government entit y will be required for export of those products. trademarks copyright ? 1999?2005 advanced micro devices, inc. all rights reserv ed. amd, the amd logo, and combinations thereof are registe red trade- marks of advanced micro devices, inc. expressflash is a trademar k of advanced micro devices, inc. product names used in this pu blication are for identification purposes only and may be tr ademarks of their respective companies. copyright ? 2006 spansion inc. all rights reserved. spansion, t he spansion logo, mirrorbit, orna nd, hd-sim, and combinations th ereof are trademarks of spansion inc. other names are for informational purposes only and may be trademarks of their respective owners. |
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